The present invention relates to power design tools, and more particularly, to a method for showing hierarchical structure for a given power intent described in a power intent description language (e.g. a formal power intent description language) with a design described in a hardware design description language, and an associated apparatus and an associated computer program product.
Conventional power design/debugging tools may be widely used by low power designers for various kinds of electronic products. According to the related art, the aforementioned conventional power design/debugging tools typically show the power design in a flat manner, and therefore, some problems may occur. For example, the user of one of the aforementioned conventional power design/debugging tools, such as a designer, cannot easily debug his/her power design since the raw information of the power design given by conventional tools is not user-friendly. As a result, conventional power design/debugging tools may result in inefficiency when designers use these tools to design or debug. Thus, a novel method is required for improving power design/debugging tools and enhancing the user experience and the design/verification environment.